1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a package configuration to provide low cost high performance electronic device packages that allows on-board testing and options for attaching electrical shielding, heat spreader or stack of multiple packages for highly integrated portable electronic products.
2. Description of the Prior Art
For conventional molded plastic packages using leadframe for interconnection substrates, packages such as QFP, SOIC, PLCC or SOJ, the IC chip and chip interconnects by either wire bonding or implementing a flip chip configuration, the packages are molded into square or rectangular body. All electrical paths are extended to outside of the molded plastic body along the perimeter of the plastic body. Since the outer lead pitch (OLP), typically 1 mm or greater, along the perimeter of the molded plastic body limits the connection density, for electronic devices that have large number of external electrical paths along the perimeters, it is generally required to make the plastic body to have a relatively large size. Presently, for a quad flat package (QFP), a practical limit is two hundred and eight (208), using 1.27 mm OLP. Furthermore, extended pins outside of the plastic body along the perimeters are very vulnerable to damage from handling or testing.
Plastic ball grid array (PBGA) was developed to address the issues caused by the limitation of the pin count for the conventional leadframe packages. In a PBGA package, the IC chip and the interconnecting wires or metal traces are bonded onto a PCB type of substrate. A plastic molding compound is used to encapsulate the IC chip and the interconnections on only one side of the substrate. All electrical signals are connected through via holes opened through the substrate to solder balls on the other side of substrate. Since the solder balls can be arranged in area array format, the number of signal connections can be much higher than that of the QFP packages. Therefore, a PBGA package that has a few hundreds of solder balls is quite common at the present packages. But, for one side molded BGA, the top and bottom structures are not symmetrical. As the bending or warping could occur throughout the hot processing steps or upon the heat cycles that occurs in the operational environment, it creates great stress onto IC chip and caused reliability vulnerability. Furthermore, all solder balls are placed under the substrate. Many of their connecting traces are routed through multi-layers inside of the motherboard, without any top surface pads. Thus, in most cases, individual PBGA cannot be probed or tested after it has been mounted on the motherboard.
For all existing molded packages, the electrical signal paths are either along the perimeters or from the bottom of molded body. For connections of these configurations, connections from the top of the molded body cannot be made for stacking or testing purposes. Therefore, a need still exits in the art to provide new and improved packaging configurations and also manufacturing procedures for resolving the above discussed problem and difficulties.
Additionally, the PBGA packages are still limited by the high cost of the substrate materials. The conventional quad flat pack (QFP) packages are not amiable to stacking to achieve a three-dimensional packaging configuration. Therefore, a need still exits in the art to provide low cost and improved packaging configurations and also manufacturing procedures for resolving the above discussed problems and difficulties.